1. Technical Field
The present invention relates to a multi-layered semiconductor apparatus formed by layered semiconductor elements.
2. Related Art
In recent years, electronic devices such as mobile phones and personal computers have become smaller, thinner, and more light-weight, and this increases the demand for smaller electronic components that have high performance or multiple functions. Along with this trend, there is a desire for smaller semiconductor apparatuses that require less area for installation and have high performance or multiple functions. In memory ICs, the demand for larger memory capacity, lighter weight, and lower cost is particularly high, and therefore various package configurations and implementation configurations are being considered for memory ICs.
For example, U.S. Pat. No. 7,115,967 aims to increase the capacity of a memory IC loaded on a package, and discloses semiconductor package in which chips having memory functions are three-dimensionally layered.
As shown by Japanese Patent Application Publication No. 2006-032379, the demand for semiconductor apparatus packages that have a memory function and a logic function in a single package is currently increasing. One technique for achieving the memory function and the logic function in a single package involves layering packages, which are implemented in flip chips formed on thin circuit boards, onto a base board.
Since packages in which the memory ICs and logic ICs are implemented independently are layered in this configuration, a change in the request function between users can be easily adapted to by changing the type of layered memory ICs and logic ICs, and this has the advantage of shortening the development time for the semiconductor package. Therefore, the future development of semiconductor packets including memory functions and logic functions is expected to involve the development of configurations in which ICs having memory functions and ICs having logic functions are layered.
However, the multi-layered semiconductor apparatus described above has the following problems. A package that includes many memory IC layers to achieve a large memory capacity has few areas from which the heat generated by the memory circuits can escape. Furthermore, in the case of a semiconductor package including a memory function and a logic function and having a three-dimensional layered configuration, the semiconductor elements reach high temperatures due to the heat generated when the logic IC operates, and this heat is of an order greater than the heat generated by the memory ICs.
If the semiconductor package cannot release enough heat, a delay occurs in the computational processing, and this causes operational errors in the semiconductor package. Even if a uniform temperature increase is achieved due to differences in the thermal expansion of materials such as silicon (Si) and an insulator used to form the semiconductor package, the semiconductor package experiences thermal stress, and even more thermal stress may be added by temperature irregularities in the heat-generating regions, which would cause thermal deformation or damage the IC elements in the package through thermal stress.
In order to observe the temperature of the semiconductor package, a technique commonly used is controlling rotation of a heat release fan based on temperature information from a thermal sensor disposed near the semiconductor package. With this technique, precise thermal control cannot be achieved since the temperature distribution within the three-dimensional layered structure cannot be observed. Accordingly, temperature control is becoming extremely important for three-dimensional layered semiconductor packages to solve the above problems relating to heat.
Therefore it is an object of an aspect of the innovations herein to provide a multi-layered semiconductor apparatus in which semiconductor elements are layered in three-dimensions, which can increase the dispersion of heat and the efficiency of heat release.